In a solid state drive (SSD) controller of a system, the error correction code (ECC) decoding time is critical for read latency. How to efficiently decode data read from NAND flash memory is an important topic for system performance.
Typically, several ECC decoding schemes are available on the system and can be used to process the read data. Each of the decoding schemes has different power consumption and decoding capability, including latency and bit error rate (BER). The system processes the read data through the decoding schemes serially to achieve an overall BER. However, the serial decoding increases the latency and power consumption for noisy data (with more error bits) because each decoding scheme takes time and consumes power to process the data. Certain applications may necessitate a particular BER while also being time critical and/or power sensitive. For at least these applications, the resulting latency and/or power consumption of the serial decoding can be unacceptable. In addition, performance of other less time critical and/or power sensitive applications can be improved by reducing the latency and/or power consumption.